From a840d623b6a70428e8b698f0116fecc38e16e668 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Tue, 20 Mar 2012 13:05:11 +0100
Subject: [PATCH 65/70] MIPS: adds dsl clocks

---
 arch/mips/lantiq/xway/sysctrl.c |   15 +++++++++++++--
 1 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
index 6771a7e..3672fc6 100644
--- a/arch/mips/lantiq/xway/sysctrl.c
+++ b/arch/mips/lantiq/xway/sysctrl.c
@@ -41,8 +41,9 @@
 #define PMU_PCI		BIT(4)
 #define PMU_DMA		BIT(5)
 #define PMU_USB0	BIT(5)
+#define PMU_EPHY	BIT(7)	/* ase */
 #define PMU_SPI		BIT(8)
-#define PMU_EPHY	BIT(7)
+#define PMU_DFE		BIT(9)
 #define PMU_EBU		BIT(10)
 #define PMU_STP		BIT(11)
 #define PMU_GPT		BIT(12)
@@ -147,7 +148,7 @@ static int ltq_pci_ext_enable(struct clk *clk)
 
 static void ltq_pci_ext_disable(struct clk *clk)
 {
-	/* enable external pci clock */
+	/* disable external pci clock (internal) */
 	ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) | (1 << 16),
 		CGU_IFCCR);
 	ltq_cgu_w32((1 << 31) | (1 << 30), CGU_PCICR);
@@ -246,6 +247,9 @@ void __init ltq_soc_init(void)
 			clkdev_add_static(CLOCK_133M, CLOCK_133M, CLOCK_133M);
 		clkdev_add_cgu("ltq_etop", "ephycgu", CGU_EPHY),
 		clkdev_add_pmu("ltq_etop", "ephy", 0, PMU_EPHY);
+		clkdev_add_pmu("ltq_dsl", NULL, 0,
+			PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
+			PMU_AHBS | PMU_DFE);
 	} else if (ltq_is_vr9()) {
 		clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(),
 			ltq_vr9_fpi_hz());
@@ -261,12 +265,19 @@ void __init ltq_soc_init(void)
 			PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM |
 			PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
 			PMU_PPE_QSB);
+		clkdev_add_pmu("ltq_dsl", NULL, 0, PMU_DFE | PMU_AHBS);
 	} else if (ltq_is_ar9()) {
 		clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),
 			ltq_ar9_fpi_hz());
 		clkdev_add_pmu("ltq_etop", "switch", 0, PMU_SWITCH);
+		clkdev_add_pmu("ltq_dsl", NULL, 0,
+			PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
+			PMU_PPE_QSB | PMU_AHBS | PMU_DFE);
 	} else {
 		clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
 			ltq_danube_io_region_clock());
+		clkdev_add_pmu("ltq_dsl", NULL, 0,
+			PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
+			PMU_PPE_QSB | PMU_AHBS | PMU_DFE);
 	}
 }
-- 
1.7.7.1

