mirror of
https://github.com/hak5/wifipineapple-openwrt.git
synced 2025-10-29 16:57:19 +00:00
mac80211: backport from trunk r48782 + required kernel patches and mt76, mwlwifi
Signed-off-by: Felix Fietkau <nbd@openwrt.org> git-svn-id: svn://svn.openwrt.org/openwrt/branches/chaos_calmer@48822 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
Felix Fietkau
@@ -36,6 +36,7 @@ struct ath9k_platform_data {
|
||||
bool tx_gain_buffalo;
|
||||
bool disable_2ghz;
|
||||
bool disable_5ghz;
|
||||
bool led_active_high;
|
||||
|
||||
int (*get_mac_revision)(void);
|
||||
int (*external_reset)(void);
|
||||
|
||||
@@ -1,6 +1,40 @@
|
||||
--- a/drivers/bcma/driver_chipcommon.c
|
||||
+++ b/drivers/bcma/driver_chipcommon.c
|
||||
@@ -190,6 +190,7 @@ u32 bcma_chipco_watchdog_timer_set(struc
|
||||
@@ -15,6 +15,8 @@
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/bcma/bcma.h>
|
||||
|
||||
+static void bcma_chipco_serial_init(struct bcma_drv_cc *cc);
|
||||
+
|
||||
static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset,
|
||||
u32 mask, u32 value)
|
||||
{
|
||||
@@ -115,6 +117,8 @@ int bcma_chipco_watchdog_register(struct
|
||||
|
||||
void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
|
||||
{
|
||||
+ struct bcma_bus *bus = cc->core->bus;
|
||||
+
|
||||
if (cc->early_setup_done)
|
||||
return;
|
||||
|
||||
@@ -129,6 +133,9 @@ void bcma_core_chipcommon_early_init(str
|
||||
if (cc->capabilities & BCMA_CC_CAP_PMU)
|
||||
bcma_pmu_early_init(cc);
|
||||
|
||||
+ if (IS_BUILTIN(CONFIG_BCM47XX) && bus->hosttype == BCMA_HOSTTYPE_SOC)
|
||||
+ bcma_chipco_serial_init(cc);
|
||||
+
|
||||
cc->early_setup_done = true;
|
||||
}
|
||||
|
||||
@@ -185,11 +192,12 @@ u32 bcma_chipco_watchdog_timer_set(struc
|
||||
ticks = 2;
|
||||
else if (ticks > maxt)
|
||||
ticks = maxt;
|
||||
- bcma_cc_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks);
|
||||
+ bcma_pmu_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks);
|
||||
} else {
|
||||
struct bcma_bus *bus = cc->core->bus;
|
||||
|
||||
if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4707 &&
|
||||
@@ -8,6 +42,232 @@
|
||||
bus->chipinfo.id != BCMA_CHIP_ID_BCM53018)
|
||||
bcma_core_set_clockmode(cc->core,
|
||||
ticks ? BCMA_CLKMODE_FAST : BCMA_CLKMODE_DYNAMIC);
|
||||
@@ -314,9 +322,9 @@ u32 bcma_chipco_gpio_pulldown(struct bcm
|
||||
return res;
|
||||
}
|
||||
|
||||
-#ifdef CONFIG_BCMA_DRIVER_MIPS
|
||||
-void bcma_chipco_serial_init(struct bcma_drv_cc *cc)
|
||||
+static void bcma_chipco_serial_init(struct bcma_drv_cc *cc)
|
||||
{
|
||||
+#if IS_BUILTIN(CONFIG_BCM47XX)
|
||||
unsigned int irq;
|
||||
u32 baud_base;
|
||||
u32 i;
|
||||
@@ -358,5 +366,5 @@ void bcma_chipco_serial_init(struct bcma
|
||||
ports[i].baud_base = baud_base;
|
||||
ports[i].reg_shift = 0;
|
||||
}
|
||||
+#endif /* CONFIG_BCM47XX */
|
||||
}
|
||||
-#endif /* CONFIG_BCMA_DRIVER_MIPS */
|
||||
--- a/drivers/bcma/driver_chipcommon_pmu.c
|
||||
+++ b/drivers/bcma/driver_chipcommon_pmu.c
|
||||
@@ -15,44 +15,44 @@
|
||||
|
||||
u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
|
||||
{
|
||||
- bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
|
||||
- bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
|
||||
- return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
|
||||
+ bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR, offset);
|
||||
+ bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_ADDR);
|
||||
+ return bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_DATA);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(bcma_chipco_pll_read);
|
||||
|
||||
void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value)
|
||||
{
|
||||
- bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
|
||||
- bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
|
||||
- bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);
|
||||
+ bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR, offset);
|
||||
+ bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_ADDR);
|
||||
+ bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_DATA, value);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(bcma_chipco_pll_write);
|
||||
|
||||
void bcma_chipco_pll_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
|
||||
u32 set)
|
||||
{
|
||||
- bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
|
||||
- bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
|
||||
- bcma_cc_maskset32(cc, BCMA_CC_PLLCTL_DATA, mask, set);
|
||||
+ bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR, offset);
|
||||
+ bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_ADDR);
|
||||
+ bcma_pmu_maskset32(cc, BCMA_CC_PMU_PLLCTL_DATA, mask, set);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(bcma_chipco_pll_maskset);
|
||||
|
||||
void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc,
|
||||
u32 offset, u32 mask, u32 set)
|
||||
{
|
||||
- bcma_cc_write32(cc, BCMA_CC_CHIPCTL_ADDR, offset);
|
||||
- bcma_cc_read32(cc, BCMA_CC_CHIPCTL_ADDR);
|
||||
- bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL_DATA, mask, set);
|
||||
+ bcma_pmu_write32(cc, BCMA_CC_PMU_CHIPCTL_ADDR, offset);
|
||||
+ bcma_pmu_read32(cc, BCMA_CC_PMU_CHIPCTL_ADDR);
|
||||
+ bcma_pmu_maskset32(cc, BCMA_CC_PMU_CHIPCTL_DATA, mask, set);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(bcma_chipco_chipctl_maskset);
|
||||
|
||||
void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
|
||||
u32 set)
|
||||
{
|
||||
- bcma_cc_write32(cc, BCMA_CC_REGCTL_ADDR, offset);
|
||||
- bcma_cc_read32(cc, BCMA_CC_REGCTL_ADDR);
|
||||
- bcma_cc_maskset32(cc, BCMA_CC_REGCTL_DATA, mask, set);
|
||||
+ bcma_pmu_write32(cc, BCMA_CC_PMU_REGCTL_ADDR, offset);
|
||||
+ bcma_pmu_read32(cc, BCMA_CC_PMU_REGCTL_ADDR);
|
||||
+ bcma_pmu_maskset32(cc, BCMA_CC_PMU_REGCTL_DATA, mask, set);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
|
||||
|
||||
@@ -60,18 +60,18 @@ static u32 bcma_pmu_xtalfreq(struct bcma
|
||||
{
|
||||
u32 ilp_ctl, alp_hz;
|
||||
|
||||
- if (!(bcma_cc_read32(cc, BCMA_CC_PMU_STAT) &
|
||||
+ if (!(bcma_pmu_read32(cc, BCMA_CC_PMU_STAT) &
|
||||
BCMA_CC_PMU_STAT_EXT_LPO_AVAIL))
|
||||
return 0;
|
||||
|
||||
- bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ,
|
||||
- BIT(BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT));
|
||||
+ bcma_pmu_write32(cc, BCMA_CC_PMU_XTAL_FREQ,
|
||||
+ BIT(BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT));
|
||||
usleep_range(1000, 2000);
|
||||
|
||||
- ilp_ctl = bcma_cc_read32(cc, BCMA_CC_PMU_XTAL_FREQ);
|
||||
+ ilp_ctl = bcma_pmu_read32(cc, BCMA_CC_PMU_XTAL_FREQ);
|
||||
ilp_ctl &= BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK;
|
||||
|
||||
- bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ, 0);
|
||||
+ bcma_pmu_write32(cc, BCMA_CC_PMU_XTAL_FREQ, 0);
|
||||
|
||||
alp_hz = ilp_ctl * 32768 / 4;
|
||||
return (alp_hz + 50000) / 100000 * 100;
|
||||
@@ -127,8 +127,8 @@ static void bcma_pmu2_pll_init0(struct b
|
||||
mask = (u32)~(BCMA_RES_4314_HT_AVAIL |
|
||||
BCMA_RES_4314_MACPHY_CLK_AVAIL);
|
||||
|
||||
- bcma_cc_mask32(cc, BCMA_CC_PMU_MINRES_MSK, mask);
|
||||
- bcma_cc_mask32(cc, BCMA_CC_PMU_MAXRES_MSK, mask);
|
||||
+ bcma_pmu_mask32(cc, BCMA_CC_PMU_MINRES_MSK, mask);
|
||||
+ bcma_pmu_mask32(cc, BCMA_CC_PMU_MAXRES_MSK, mask);
|
||||
bcma_wait_value(cc->core, BCMA_CLKCTLST,
|
||||
BCMA_CLKCTLST_HAVEHT, 0, 20000);
|
||||
break;
|
||||
@@ -140,7 +140,7 @@ static void bcma_pmu2_pll_init0(struct b
|
||||
|
||||
/* Flush */
|
||||
if (cc->pmu.rev >= 2)
|
||||
- bcma_cc_set32(cc, BCMA_CC_PMU_CTL, BCMA_CC_PMU_CTL_PLL_UPD);
|
||||
+ bcma_pmu_set32(cc, BCMA_CC_PMU_CTL, BCMA_CC_PMU_CTL_PLL_UPD);
|
||||
|
||||
/* TODO: Do we need to update OTP? */
|
||||
}
|
||||
@@ -195,9 +195,9 @@ static void bcma_pmu_resources_init(stru
|
||||
|
||||
/* Set the resource masks. */
|
||||
if (min_msk)
|
||||
- bcma_cc_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk);
|
||||
+ bcma_pmu_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk);
|
||||
if (max_msk)
|
||||
- bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
|
||||
+ bcma_pmu_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
|
||||
|
||||
/*
|
||||
* Add some delay; allow resources to come up and settle.
|
||||
@@ -269,23 +269,33 @@ static void bcma_pmu_workarounds(struct
|
||||
|
||||
void bcma_pmu_early_init(struct bcma_drv_cc *cc)
|
||||
{
|
||||
+ struct bcma_bus *bus = cc->core->bus;
|
||||
u32 pmucap;
|
||||
|
||||
- pmucap = bcma_cc_read32(cc, BCMA_CC_PMU_CAP);
|
||||
+ if (cc->core->id.rev >= 35 &&
|
||||
+ cc->capabilities_ext & BCMA_CC_CAP_EXT_AOB_PRESENT) {
|
||||
+ cc->pmu.core = bcma_find_core(bus, BCMA_CORE_PMU);
|
||||
+ if (!cc->pmu.core)
|
||||
+ bcma_warn(bus, "Couldn't find expected PMU core");
|
||||
+ }
|
||||
+ if (!cc->pmu.core)
|
||||
+ cc->pmu.core = cc->core;
|
||||
+
|
||||
+ pmucap = bcma_pmu_read32(cc, BCMA_CC_PMU_CAP);
|
||||
cc->pmu.rev = (pmucap & BCMA_CC_PMU_CAP_REVISION);
|
||||
|
||||
- bcma_debug(cc->core->bus, "Found rev %u PMU (capabilities 0x%08X)\n",
|
||||
- cc->pmu.rev, pmucap);
|
||||
+ bcma_debug(bus, "Found rev %u PMU (capabilities 0x%08X)\n", cc->pmu.rev,
|
||||
+ pmucap);
|
||||
}
|
||||
|
||||
void bcma_pmu_init(struct bcma_drv_cc *cc)
|
||||
{
|
||||
if (cc->pmu.rev == 1)
|
||||
- bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
|
||||
- ~BCMA_CC_PMU_CTL_NOILPONW);
|
||||
+ bcma_pmu_mask32(cc, BCMA_CC_PMU_CTL,
|
||||
+ ~BCMA_CC_PMU_CTL_NOILPONW);
|
||||
else
|
||||
- bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
|
||||
- BCMA_CC_PMU_CTL_NOILPONW);
|
||||
+ bcma_pmu_set32(cc, BCMA_CC_PMU_CTL,
|
||||
+ BCMA_CC_PMU_CTL_NOILPONW);
|
||||
|
||||
bcma_pmu_pll_init(cc);
|
||||
bcma_pmu_resources_init(cc);
|
||||
@@ -472,8 +482,8 @@ u32 bcma_pmu_get_cpu_clock(struct bcma_d
|
||||
static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset,
|
||||
u32 value)
|
||||
{
|
||||
- bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
|
||||
- bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);
|
||||
+ bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR, offset);
|
||||
+ bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_DATA, value);
|
||||
}
|
||||
|
||||
void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid)
|
||||
@@ -497,20 +507,20 @@ void bcma_pmu_spuravoid_pllupdate(struct
|
||||
bus->chipinfo.id == BCMA_CHIP_ID_BCM53572) ? 6 : 0;
|
||||
|
||||
/* RMW only the P1 divider */
|
||||
- bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
|
||||
+ bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR,
|
||||
BCMA_CC_PMU_PLL_CTL0 + phypll_offset);
|
||||
- tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
|
||||
+ tmp = bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_DATA);
|
||||
tmp &= (~(BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK));
|
||||
tmp |= (bcm5357_bcm43236_p1div[spuravoid] << BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT);
|
||||
- bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
|
||||
+ bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_DATA, tmp);
|
||||
|
||||
/* RMW only the int feedback divider */
|
||||
- bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
|
||||
+ bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR,
|
||||
BCMA_CC_PMU_PLL_CTL2 + phypll_offset);
|
||||
- tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
|
||||
+ tmp = bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_DATA);
|
||||
tmp &= ~(BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK);
|
||||
tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT;
|
||||
- bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
|
||||
+ bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_DATA, tmp);
|
||||
|
||||
tmp = BCMA_CC_PMU_CTL_PLL_UPD;
|
||||
break;
|
||||
@@ -646,7 +656,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
|
||||
break;
|
||||
}
|
||||
|
||||
- tmp |= bcma_cc_read32(cc, BCMA_CC_PMU_CTL);
|
||||
- bcma_cc_write32(cc, BCMA_CC_PMU_CTL, tmp);
|
||||
+ tmp |= bcma_pmu_read32(cc, BCMA_CC_PMU_CTL);
|
||||
+ bcma_pmu_write32(cc, BCMA_CC_PMU_CTL, tmp);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(bcma_pmu_spuravoid_pllupdate);
|
||||
--- a/drivers/bcma/driver_chipcommon_sflash.c
|
||||
+++ b/drivers/bcma/driver_chipcommon_sflash.c
|
||||
@@ -38,6 +38,7 @@ static const struct bcma_sflash_tbl_e bc
|
||||
@@ -18,27 +278,6 @@
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
--- a/drivers/bcma/driver_gpio.c
|
||||
+++ b/drivers/bcma/driver_gpio.c
|
||||
@@ -229,6 +229,7 @@ int bcma_gpio_init(struct bcma_drv_cc *c
|
||||
case BCMA_CHIP_ID_BCM4707:
|
||||
case BCMA_CHIP_ID_BCM5357:
|
||||
case BCMA_CHIP_ID_BCM53572:
|
||||
+ case BCMA_CHIP_ID_BCM47094:
|
||||
chip->ngpio = 32;
|
||||
break;
|
||||
default:
|
||||
--- a/drivers/bcma/host_pci.c
|
||||
+++ b/drivers/bcma/host_pci.c
|
||||
@@ -294,7 +294,7 @@ static const struct pci_device_id bcma_p
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) },
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) },
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4360) },
|
||||
- { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4365) },
|
||||
+ { PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, 0x4365, PCI_VENDOR_ID_DELL, 0x0016) },
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43a0) },
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43a9) },
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43aa) },
|
||||
--- a/drivers/bcma/scan.c
|
||||
+++ b/drivers/bcma/scan.c
|
||||
@@ -98,6 +98,9 @@ static const struct bcma_device_id_name
|
||||
@@ -51,6 +290,32 @@
|
||||
{ BCMA_CORE_DEFAULT, "Default" },
|
||||
};
|
||||
|
||||
@@ -315,6 +318,8 @@ static int bcma_get_next_core(struct bcm
|
||||
switch (core->id.id) {
|
||||
case BCMA_CORE_4706_MAC_GBIT_COMMON:
|
||||
case BCMA_CORE_NS_CHIPCOMMON_B:
|
||||
+ case BCMA_CORE_PMU:
|
||||
+ case BCMA_CORE_GCI:
|
||||
/* Not used yet: case BCMA_CORE_OOB_ROUTER: */
|
||||
break;
|
||||
default:
|
||||
--- a/drivers/net/wireless/b43/main.c
|
||||
+++ b/drivers/net/wireless/b43/main.c
|
||||
@@ -1215,10 +1215,10 @@ void b43_wireless_core_phy_pll_reset(str
|
||||
case B43_BUS_BCMA:
|
||||
bcma_cc = &dev->dev->bdev->bus->drv_cc;
|
||||
|
||||
- bcma_cc_write32(bcma_cc, BCMA_CC_CHIPCTL_ADDR, 0);
|
||||
- bcma_cc_mask32(bcma_cc, BCMA_CC_CHIPCTL_DATA, ~0x4);
|
||||
- bcma_cc_set32(bcma_cc, BCMA_CC_CHIPCTL_DATA, 0x4);
|
||||
- bcma_cc_mask32(bcma_cc, BCMA_CC_CHIPCTL_DATA, ~0x4);
|
||||
+ bcma_cc_write32(bcma_cc, BCMA_CC_PMU_CHIPCTL_ADDR, 0);
|
||||
+ bcma_cc_mask32(bcma_cc, BCMA_CC_PMU_CHIPCTL_DATA, ~0x4);
|
||||
+ bcma_cc_set32(bcma_cc, BCMA_CC_PMU_CHIPCTL_DATA, 0x4);
|
||||
+ bcma_cc_mask32(bcma_cc, BCMA_CC_PMU_CHIPCTL_DATA, ~0x4);
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_B43_SSB
|
||||
--- a/include/linux/bcma/bcma.h
|
||||
+++ b/include/linux/bcma/bcma.h
|
||||
@@ -151,6 +151,8 @@ struct bcma_host_ops {
|
||||
@@ -70,3 +335,110 @@
|
||||
#define BCMA_CHIP_ID_BCM53018 53018
|
||||
|
||||
/* Board types (on PCI usually equals to the subsystem dev id) */
|
||||
--- a/include/linux/bcma/bcma_driver_chipcommon.h
|
||||
+++ b/include/linux/bcma/bcma_driver_chipcommon.h
|
||||
@@ -217,6 +217,11 @@
|
||||
#define BCMA_CC_CLKDIV_JTAG_SHIFT 8
|
||||
#define BCMA_CC_CLKDIV_UART 0x000000FF
|
||||
#define BCMA_CC_CAP_EXT 0x00AC /* Capabilities */
|
||||
+#define BCMA_CC_CAP_EXT_SECI_PRESENT 0x00000001
|
||||
+#define BCMA_CC_CAP_EXT_GSIO_PRESENT 0x00000002
|
||||
+#define BCMA_CC_CAP_EXT_GCI_PRESENT 0x00000004
|
||||
+#define BCMA_CC_CAP_EXT_SECI_PUART_PRESENT 0x00000008 /* UART present */
|
||||
+#define BCMA_CC_CAP_EXT_AOB_PRESENT 0x00000040
|
||||
#define BCMA_CC_PLLONDELAY 0x00B0 /* Rev >= 4 only */
|
||||
#define BCMA_CC_FREFSELDELAY 0x00B4 /* Rev >= 4 only */
|
||||
#define BCMA_CC_SLOWCLKCTL 0x00B8 /* 6 <= Rev <= 9 only */
|
||||
@@ -351,12 +356,12 @@
|
||||
#define BCMA_CC_PMU_RES_REQTS 0x0640 /* PMU res req timer sel */
|
||||
#define BCMA_CC_PMU_RES_REQT 0x0644 /* PMU res req timer */
|
||||
#define BCMA_CC_PMU_RES_REQM 0x0648 /* PMU res req mask */
|
||||
-#define BCMA_CC_CHIPCTL_ADDR 0x0650
|
||||
-#define BCMA_CC_CHIPCTL_DATA 0x0654
|
||||
-#define BCMA_CC_REGCTL_ADDR 0x0658
|
||||
-#define BCMA_CC_REGCTL_DATA 0x065C
|
||||
-#define BCMA_CC_PLLCTL_ADDR 0x0660
|
||||
-#define BCMA_CC_PLLCTL_DATA 0x0664
|
||||
+#define BCMA_CC_PMU_CHIPCTL_ADDR 0x0650
|
||||
+#define BCMA_CC_PMU_CHIPCTL_DATA 0x0654
|
||||
+#define BCMA_CC_PMU_REGCTL_ADDR 0x0658
|
||||
+#define BCMA_CC_PMU_REGCTL_DATA 0x065C
|
||||
+#define BCMA_CC_PMU_PLLCTL_ADDR 0x0660
|
||||
+#define BCMA_CC_PMU_PLLCTL_DATA 0x0664
|
||||
#define BCMA_CC_PMU_STRAPOPT 0x0668 /* (corerev >= 28) */
|
||||
#define BCMA_CC_PMU_XTAL_FREQ 0x066C /* (pmurev >= 10) */
|
||||
#define BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK 0x00001FFF
|
||||
@@ -566,6 +571,7 @@
|
||||
* Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
|
||||
*/
|
||||
struct bcma_chipcommon_pmu {
|
||||
+ struct bcma_device *core; /* Can be separated core or just ChipCommon one */
|
||||
u8 rev; /* PMU revision */
|
||||
u32 crystalfreq; /* The active crystal frequency (in kHz) */
|
||||
};
|
||||
@@ -663,6 +669,19 @@ struct bcma_drv_cc_b {
|
||||
#define bcma_cc_maskset32(cc, offset, mask, set) \
|
||||
bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set))
|
||||
|
||||
+/* PMU registers access */
|
||||
+#define bcma_pmu_read32(cc, offset) \
|
||||
+ bcma_read32((cc)->pmu.core, offset)
|
||||
+#define bcma_pmu_write32(cc, offset, val) \
|
||||
+ bcma_write32((cc)->pmu.core, offset, val)
|
||||
+
|
||||
+#define bcma_pmu_mask32(cc, offset, mask) \
|
||||
+ bcma_pmu_write32(cc, offset, bcma_pmu_read32(cc, offset) & (mask))
|
||||
+#define bcma_pmu_set32(cc, offset, set) \
|
||||
+ bcma_pmu_write32(cc, offset, bcma_pmu_read32(cc, offset) | (set))
|
||||
+#define bcma_pmu_maskset32(cc, offset, mask, set) \
|
||||
+ bcma_pmu_write32(cc, offset, (bcma_pmu_read32(cc, offset) & (mask)) | (set))
|
||||
+
|
||||
extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks);
|
||||
|
||||
extern u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc);
|
||||
--- a/drivers/bcma/bcma_private.h
|
||||
+++ b/drivers/bcma/bcma_private.h
|
||||
@@ -47,7 +47,6 @@ void bcma_core_chipcommon_early_init(str
|
||||
void bcma_core_chipcommon_init(struct bcma_drv_cc *cc);
|
||||
void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable);
|
||||
#ifdef CONFIG_BCMA_DRIVER_MIPS
|
||||
-void bcma_chipco_serial_init(struct bcma_drv_cc *cc);
|
||||
extern struct platform_device bcma_pflash_dev;
|
||||
#endif /* CONFIG_BCMA_DRIVER_MIPS */
|
||||
|
||||
--- a/drivers/bcma/driver_gpio.c
|
||||
+++ b/drivers/bcma/driver_gpio.c
|
||||
@@ -229,6 +229,7 @@ int bcma_gpio_init(struct bcma_drv_cc *c
|
||||
case BCMA_CHIP_ID_BCM4707:
|
||||
case BCMA_CHIP_ID_BCM5357:
|
||||
case BCMA_CHIP_ID_BCM53572:
|
||||
+ case BCMA_CHIP_ID_BCM47094:
|
||||
chip->ngpio = 32;
|
||||
break;
|
||||
default:
|
||||
--- a/drivers/bcma/driver_mips.c
|
||||
+++ b/drivers/bcma/driver_mips.c
|
||||
@@ -328,12 +328,9 @@ static void bcma_core_mips_flash_detect(
|
||||
|
||||
void bcma_core_mips_early_init(struct bcma_drv_mips *mcore)
|
||||
{
|
||||
- struct bcma_bus *bus = mcore->core->bus;
|
||||
-
|
||||
if (mcore->early_setup_done)
|
||||
return;
|
||||
|
||||
- bcma_chipco_serial_init(&bus->drv_cc);
|
||||
bcma_core_mips_flash_detect(mcore);
|
||||
|
||||
mcore->early_setup_done = true;
|
||||
--- a/drivers/bcma/host_pci.c
|
||||
+++ b/drivers/bcma/host_pci.c
|
||||
@@ -294,7 +294,7 @@ static const struct pci_device_id bcma_p
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) },
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) },
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4360) },
|
||||
- { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4365) },
|
||||
+ { PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, 0x4365, PCI_VENDOR_ID_DELL, 0x0016) },
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43a0) },
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43a9) },
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43aa) },
|
||||
|
||||
Reference in New Issue
Block a user